The field of the invention relates to topology of power converters. In particular, the field of the invention relates to fault-tolerant topology for multilevel T-type power converters.
A power converter is the most fundamental functional unit in all solid-state power conversion systems, and therefore its fault-tolerant capability plays a critical role in the systems' reliability. Among multilevel power converters, the T-Type neutral-point-clamped (NPC) converter has been regarded as a very promising breed of high-performance multilevel inverters in industrial applications, because of the relatively lower number of switching devices used and higher efficiency compared with the conventional I-Type NPC inverters.
Like other types of multilevel converters, T-Type NPC inverters are not immune to switching device faults, for example, insulated-gate bipolar transistor (IGBT) open-circuit or short-circuit faults. Such switching device faults could cause catastrophic system failures if no fault-tolerant solution is provided when such inverters are applied in safety-critical applications, such as electric vehicles (EV), hybrid-electric vehicles (HEV), Uninterruptable Power Supplies (UPSs), solar inverters, and the like. Although the T-Type NPC inverter has certain inherent fault-tolerant capability due to its unique topology, the output voltage and linear operating range will be derated significantly during fault-tolerant operation, which is not allowed in some applications (e.g., UPS, EV, etc.) where rated voltage is a stringent requirement. Therefore, it would be of great significance to improve the inverter topology with satisfactory fault-tolerant characteristics, to guarantee rated output voltages under faulty conditions.
The existing solution for the fault-tolerant operation of T-Type NPC inverters is mainly achieved by paralleling one or three redundant inverter legs. This does ensure a rated voltage output under inverter faulty condition, but at a much higher system cost with decreased efficiency due to much more additional semiconductor devices employed. Rather, most of the redundant semiconductor devices in the existing fault-tolerant topology idle in the circuit without contribution to system performance improvement under healthy conditions. This degrades system efficiency due to additional switching and conduction losses.
Another previous attempt to improve fault-tolerance of T-Type NPC converters uses a software control strategy by using the limited inherent fault-tolerant capabilities of the T-Type converters. The drawback of this fault-tolerant solution is the derated output voltage during post-fault operation.